1. Field of the Invention
The present invention relates to a technology of receiving an optical signal in optical data communication by differential quadrature phase shift keying (DQPSK) modulation.
2. Description of the Related Art
In the use of data communication systems in recent years, which is typified by the Internet, a communication system to meet growing demands for data communication has been studied. An optical communication system employing intensity modulation differential quadrature phase shift keying (IM-DQPSK) has been considered as such a communication system that improves frequency use efficiency. Such a technology is described in, for example, IEEE Photon. Technol. Lett., vol. 15, pp. 473-475, March 2003, titled “Transmission of 25-Gb/S RZ-DQPSK signals with 25-GHz channel spacing over 1000 km of SMF-28 fiber”, by P. S. Cho, V. S. Grioryan, Y. A. Godin, A. Salamon, and Y. Achiam, IEEE Photon. Technol. Lett., vol. 15, pp. 769-771, May 2003, titled “Transmission of 8×20 Gb/S DQPSK signals with 25-GHz channel spacing over 310 km SMF with 0.8 b/s/Hz spectral efficiency” by H. Kim, and R-J. Essiambre, and Technical Digest of OF2004, postdeadline paper, PDP 38) titled “1.14 b/s/Hz spectrally efficient 50×85.4 Gb/s transmission over 300 km using copolarized CS-RZ DQPSK signals” by N. Yoshikane and I. Morita.
FIG. 25 depicts a conventional optical signal transceiver (optical transponder) employing IM-DQPSK. As shown in FIG. 25, the optical signal transceiver includes a framer (framer-LSI) 100, an optical receiving unit (40 GOR) 101, a serializing unit (SER) 102, a demultiplexing unit (DEMUX) 103, a precoder (DQPSK precoder) 104, a DQPSK modulating unit (40G DQPSK OS) 105, an optical transmitting unit (40G OS) 106, a parallelizing unit (DES) 107, a multiplexing unit (MUX) 108, and a receiving/demodulating unit (40G DQPSK OR) 109.
The DQPSK modulating unit 105, of which the outline internal structure is shown above in FIG. 25, has a distribution feedback semiconductor laser (DFB-LD) 111, a phase modulator 112, an intensity modulator 113, and drivers. The phase modulator 112 includes phase modulators 114, 115, and a π/2 phase shifting unit. The receiving/demodulating unit 109, of which the outline internal structure is shown below in FIG. 25, has a π/4 delay interferometer 116, a −π/4 delay interferometer 117, photodiodes (PD), which are photoelectric conversion elements, and an amplifier (amp).
When data of 40 Gb/s is converted into an optical signal, and is modulated by DQPSK for transmission/reception, an optical signal from the client side is received by the optical receiving unit 101, where the signal is converted into an electrical signal and is also parallelized into 16 parallel signals (2.5 Gb/s×16=40 Gb/s) that are then put into the framer 100. The “b/s” expressing the unit of transfer rate is omitted from FIG. 25. The framer 100 has a function of executing a mapping process and a demapping process on a frame conforming to a transmission method of synchronous optical network (SONET), synchronous digital hierarchy (SDH), optical transport network (OTN), etc., using converted 16 parallel data.
A frame process by the framer 100 produces parallel data of 2.7 Gb/s×16, which is serialized by the serializing unit 102 into serial data of 43 Gb/s. The serial data and a clock signal of 21.5 Gb/s are put into the demultiplexing unit 103, where the input data is demultiplexed into signals lk, Qk of 21.5 Gb/S at the ratio of 1:2. The signals lk, Qk are then put into the precoder 104 that converts the input signals into signals ηk, ρk according to a given logic, and puts the signals ηk, ρk into the DQPSK modulating unit 105.
The precoder 104 converts the input in-phase signals lk and quadrature signals Qk into the signals ηk, ρk, as described above. The precoder 104 is composed of a logic gate circuit that is a combination of OR circuits, AND circuits, inhibit circuits, etc. The signals ηk, ρk converted by the precoder 104 (21.5G data) are put into the DQPSK modulating unit 105, where the signals ηk, ρk are converted into a DQPSK optical signal, and is sent out to the network side. In the DQPSK modulating unit 105, output light from the distribution feedback semiconductor laser 111 is divided into two branches of light. One branch of light is put into the phase modulator 114, and the other branch of light is shifted in phase by π/2 and is put into the phase modulator 115. Both branches of light are modulated in phase according to the signals ηk, ρk of 21.5 Gb/S from the precoder 104, and synthesized, then put into the intensity modulator 113, which modulates the input signal in intensity using a clock signal of 21.5 GHz, and sends out the modulated signal as an IM-DQPSK signal of 43 Gb/s. Generally, the phase modulators 114, 115 and the intensity modulator 113 in the DQPSK modulating unit 105 each includes, for example, a Mach-Zehnder interferometer composed of electro-optical effect elements made of LiNbO3, etc.
A DQPSK optical signal from the network side is put into the receiving/demodulating unit 109, where the input optical signal is divided into two branched optical signals. On branched signal is put into the π/4 delay interferometer 116, and the other branched signal is put into the −π/4 delay interferometer 117. Each delay interferometer 116, 117 has two optical waveguides offering different lengths of light paths, which give the input modulated optical signal a delay τ equivalent to one symbol of the signal. The delay interferometer 116 has a π/4 phase unit on an arm, and the delay interferometer 117 has a −π/4 phase unit on an arm. The optical signal from the arm of each delay interferometer 116, 117 is put into a pair of light-receiving elements (PD) via an output side coupler. The light-receiving elements convert the optical signals photoelectrically, after which the delay interferometer 116 puts out an in-phase signal lk, and the delay interferometer 117 puts out quadrature signal Qk.
The multiplexing unit 108 multiplexes the signals lk, Qk of 21.5 Gb/s from the receiving/demodulating unit 109, and puts the multiplexed signals of 43 Gb/s and a clock signal of 21.5 Gb/s into the parallelizing unit 107, which parallelizes the input signals into parallel signals of 2.7 Gb/s×16, and puts the parallel signals into the framer 100. The framer 100 puts parallel signals of 2.5 Gb/s×16, which are demapped from a frame conforming to the transmission method of SONET, SDH, OTU, etc., into the optical transmitting unit 106, which serializes the input signals, converts the serialized signals into optical signal of 40 Gb/s, and sends the optical signal to the client side. While the parallelizing unit 107 parallelizes input signals into parallel signals of 2.7 Gb/s×16 and the signals are then processed in the framer 100 in the same parallel signal number of 2.7 Gb/s×16 after the parallelization, the parallel signal number after the parallelization may be a different parallel signal number of, for example, 10.4 Gb/s×16, thus the process in the framer 100 may be executed in the same parallel signal number of 10.4 Gb/s×16.
Such an optical communication system is proposed that employs a Mach-Zehnder interferometer as optical signal modulating and demodulating units operated by DMPSK with phase number M=2n. When n=2, the modulating and demodulating units in this system becomes the same as the one described above that are operated by DQPSK (for example, Japanese Patent Application No. 2004-516743). Another known optical signal communication system is such that a phase modulated optical signal is modulated in intensity by a clock signal, and is transmitted to the reception side, where the clock signal is reproduced based on an intensity modulation element (for example, Japanese Patent Application No. 2004-533163).
FIG. 26 depicts a structure of main units at the optical signal transmission and reception sides in the structure of the optical signal transceiver shown in FIG. 25. 121 denotes a transmitting/processing unit (OTN LSI), 122 denotes an optical modulation processing unit (43G NB Mod (Rx side)), 123 denotes an optical signal receiving/processing unit, and 124 denotes an receiving/processing unit (OTN LSI). An SFI-5 interface conforms to 40 Gb/s serdes framer interface standard specified by optical interface forum (OIF) standard OIF-SFI5-01.02. The SFI-5 interface is a parallel signal interface that connects the transmitting/processing unit 121 to the optical modulation processing unit 122, and that connects the optical signal receiving/processing unit 123 to the receiving/processing unit 124. The type of the interface connecting the transmitting/processing unit 121 to the optical modulation processing unit 122 and connecting the optical signal receiving/processing unit 123 to the receiving/processing unit 124 is not limited to SFI-5, but another type of a signal interface equivalent to the SFI-5 interface may be employed.
The transmitting/processing unit 121 includes the framer 100. The optical modulation processing unit 122 includes the serializing unit SER, the demultiplexing unit 1:2 DMUX, drivers that puts data ηk, ρk that are separated by the demultiplexing unit 1:2 DMUX, into the phase modulator to control the phase modulator, the distribution feedback semiconductor laser DFG-LD, the phase modulator, and the intensity modulator. An intensity modulated DQPSK signal output from the intensity modulator (e.g., IM-DQPSK signal including carrier suppressed return-to-zero (CSRZ)-DQPSK signal and return-to-zero (RZ)-DQPSK signal) is transmitted in the from of {lk, Qk}, {lK+1, Qk+1} . . . , which is expressed as kth data, (k+1)th data, (K+2)th data . . . on the time axis. In other words, one symbol of the IM-DQPSK optical signal includes two bits data represented as {lk, Qk}, {lK+1, Qk+1} . . . .
The optical signal receiving/processing unit 123 includes the π/4 and/−π/4 delay interferometers, photoelectric conversion elements PD, amplifiers amp, the multiplexing unit CDR+2:1 MUX that performs clock/data recovery and data multiplexing, and the parallelizing unit De-serializer. This configuration is equivalent to the configuration shown in FIG. 25 that includes the π/4 and −π/4 delay interferometers 116, 117, photoelectric conversion elements PD, amplifiers amp, the multiplexing unit 108, and the parallelizing unit 107. The clock/data recovering and multiplexing unit CDR+2:1 MUX and the parallelizing unit De-serializer are each provided as an integrated circuit. The receiving/processing unit 124 is equivalent to the framer 100 and the optical transmitting unit 106 shown in FIG. 25.
In the optical signal receiving/processing unit 123, photoelectrically converted signals Ak, Ak+1 . . . from the π/4 delay interferometer and photoelectrically converted signals Bk, Bk+1 . . . from the −π/4 delay interferometer are multiplex at the clock/data recovering and multiplexing unit CDR+2:1 MUX into signals in the form of Ak, Bk, Ak+1 . . . . The multiplexed signals are transferred to the parallelizing unit De-serializer, which converts the received signals into 16 parallel signals, and transfers the parallel signals to the receiving/processing unit 124 including the framer (see FIG. 25) via the SFI-5 interface. The order of arrangement of the parallelized 16 signals transferred to the receiving/processing unit 124 is either a combination of Case 1 and a Case 2 or of a Case 3 and a Case 4 selected from Cases 1, 2, 3, 4, according to parallelization timing.
FIG. 27 depicts reception states when signal are in states of (a), (b), (C) shown in FIG. 26. FIG. 27A depicts a reception state of signals at the A channel (Ach) and the B channel (Bch) of the optical signal receiving/processing unit 123 under various conditions. This signal reception is carried out on the assumption that a π/2 phase shifter included in the phase modulator in the optical signal transmitting unit 122 shown in FIG. 26 is capable of keeping a phase difference between an in-phase signal and a quadrature signal at π/2. In FIG. 27A, a double circle mark represents a desired reception state, and a circle mark indicates that a signal either at the A channel or B channel is logically reversed to a signal in the desired reception state. A triangular mark indicates that a received signal is in a state of logical reversion and bit swap, and a diamond mark indicates a signal in a state of bit swap. A cross mark indicates that both A and B channels put out the in-phase elements or transverse elements of a DQPSK signal, which means a condition where such a reception process as synchronized data capturing is impossible.
FIG. 27 depicts a reception state at the 16 parallel signal interface between the parallelizing unit of the optical signal receiving/processing unit 123 and the receiving/processing unit 124. Photoelectric conversion, clock/data recovery, and multiplexing performed in the optical signal receiving/processing unit 123 and signal arrangement by the parallelizing unit produce parallel signals ordered in the arrangements of any one of the Case 1 to Case 4. The Cases 3, 4 represent the arrangement of signals that the signals are shifted by one bit against the signals in the arrangement of the Cases 1, 2. Because of this, the signals arranged as the Cases 1, 2 are received in the reception state illustrated in FIG. 27B, while the signals arranged as the Cases 3, 4 are received in the reception state illustrated in FIG. 27C. In this case, as in the case of FIG. 27A, signal reception occurs in each reception state marked with a circle, triangular, diamond, cross, and double circle that represents a desired reception state.
As described above, a desired reception state marked with a double circle enables a normal optical signal reception process, thus allowing the establishment of frame synchronization. Signal reception occurring in a state other than the desired state, however, renders synchronous frame capturing impossible, thus makes the normal reception process impossible. Even if the optical signal receiving/processing unit 123 is set to a desirable reception state by setting the function of each unit of the signal receiving/processing unit 123 in detail at the initial startup, secular change or temperature change may changes the operational state of each unit, which requires resetting. Even if a reception state at the optical signal receiving/processing unit 123 is determined to become the state illustrated in FIG. 27A, the 16 parallel signal interface between the optical signal receiving/processing unit 123 and the receiving/processing unit 124 shows two possible reception states illustrated in FIGS. 27B and 27C.